ASIC/SOC CAD Engineer
MatX
<p><strong>What MatX Is Building</strong></p> <p>MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow, including construction and sign-off</li> <li>Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights</li> <li>Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results</li> <li>Work with EDA tool vendors to drive issues and enhancements to closure</li> <li>Train and support flow users and resolve any issues they might face</li> <li>Manage licenses, compute, and storage and optimize for efficiency and cost</li> <li>May include some development and support of the front-end CAD flow</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>Bachelor of Science in Electrical Engineering or equivalent</li> <li>Minimum 8 years of industry experience in ASIC Physical Design</li> <li>Great interpersonal and communication skills</li> <li>Strong proficiency in programming languages such as Perl, Python, and TCL</li> <li>Expertise developing/using industry-standard ASIC tools and methodologies for construction (e.g. partitioning, floorplanning, synthesis, place &amp; route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification)</li> <li>This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday</li> </ul> <p><strong data-start="1090" data-end="1118">Bonus Points If You Have</strong></p> <ul> <li>8 years of industry experience in ASIC Physical Design and/or CAD</li> <li>Experience with EDA license management, LSF and equivalent job schedulers, and cloud-based silicon development is a big plus</li> </ul> <p><strong>Compensation</strong></p> <p>The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.</p> <ul> <li>Early Career - $120,000 - $250,000 + equity</li> <li>Mid Career - $175,000 - $362,500 + equity</li> <li>Senior Career - $250,000 - $475,000 + equity</li> </ul> <p><strong>What We Offer</strong></p> <ul> <li><strong>A Stake in our success&nbsp;</strong>A flexible cash equity compensation mix that fits your needs</li> <li><strong>Health &amp; Wellness </strong>Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)</li> <li><strong>Time To Recharge&nbsp;</strong>4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year</li> <li><strong>Support to Parents&l