ASIC/SOC Silicon Physical Design Engineer
MatX
<p><strong>What MatX Is Building</strong></p> <p>MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Contribute to MatX’s Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII</li> <li>Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place &amp; route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification)</li> <li>Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout</li> <li>Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>Bachelor of Science in Electrical Engineering or equivalent</li> <li>Minimum 8 years of industry experience in ASIC Physical Design</li> <li>Great interpersonal and communication skills</li> <li>Strong proficiency in programming languages such as Perl, Python, and TCL</li> <li>Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL to production silicon</li> <li>Experience collaborating with Design, Verification, and DFT teams to structure, partition, and optimize designs for PPA through sign-off</li> </ul> <p><strong>Bonus Points If You Have</strong></p> <ul> <li>8 years of industry experience in ASIC Physical Design</li> <li>Experience working with third-party Design Services partners</li> </ul> <p><strong>Compensation</strong></p> <p>The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.</p> <ul> <li>Early Career - $120,000 - $250,000 + equity</li> <li>Mid Career - $175,000 - $362,500 + equity</li> <li>Senior Career - $250,000 - $475,000 + equity</li> </ul> <p><strong>What We Offer</strong></p> <ul> <li><strong>A Stake in our success&nbsp;</strong>A flexible cash equity compensation mix that fits your needs</li> <li><strong>Heath &amp; Wellness&nbsp;</strong>Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)</li> <li><strong>Time To Recharge&nbsp;</strong>4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year</li> <li><strong>Support to Parents</strong>&nbsp;Up to 12 weeks of paid parental leave, regardless of your path to parenthood</li> <li><strong>Learning &amp; Development&nbsp;</strong>$1,500 yearly towards your professional development e.g. conf