Senior SoC Power Analysis & Optimization Engineer
MatX
<p><strong>What MatX Is Building</strong></p> <p>MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Develop and maintain power estimation methodologies for AI accelerator SoCs.</li> <li>Build and calibrate energy models for early architectural exploration, design trade-off analysis, and power target definition.</li> <li>Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems.</li> <li>Analyze AI workloads and application use cases to identify opportunities for dynamic and static power reduction.</li> <li>Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset, and other SoC subsystems.</li> <li>Collaborate with architects and RTL designers to implement power-efficient microarchitecture and RTL improvements.</li> <li>Work with physical design teams to evaluate implementation-related power trade-offs.</li> <li>Define representative workloads and sign-off scenarios to improve power analysis coverage.</li> <li>Develop automation, scripts, dashboards, and heuristics to accelerate power analysis and root-cause investigation.</li> <li>Present power analysis results, optimization proposals, and design recommendations to cross-functional teams.</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>BS or MS in Electrical Engineering, Computer Engineering, or related field.</li> <li>8+ years of industry experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design.</li> <li>Strong understanding of computer architecture and SoC design.</li> <li>Experience with ASIC low-power design techniques.</li> <li>Experience performing RTL and gate-level power analysis.</li> <li>Strong analytical and debugging skills.</li> <li>Experience with Python, Perl, or similar scripting languages.</li> <li>Ability to work independently in a fast-paced environment.</li> <li>Excellent communication and cross-functional collaboration skills.</li> </ul> <p><strong>Bonus Points If You Have</strong></p> <ul> <li>RTL development experience using Verilog/SystemVerilog.</li> <li>Experience with one or more of the following:</li> <li>Experience with clock distribution, multiple clock domains, clock gating, and power-aware RTL design.</li> <li>Experience with synthesis, static timing analysis, place-and-route, and implementation flows.</li> <li>Experience using power analysis tools (or equivalent tools) such as:</li> <li>Experience developing power models, budgeting methodologies, and projection flows.</li> <li>Experience analyzing large power datasets using scripting and data analytics.</li> <li>Experience with power management techniques including:</li> <li>Experience correlating pre-silicon power estimates with silicon measurements is a plus.</li> <li>Experience with AI workload characterization and power-performance analysis is a plus.</li> </ul> <p><strong>Compensation</strong