SOC Integration Engineer
MatX
<p><strong>What MatX Is Building</strong></p> <p>MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design.</li> <li>Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL.</li> <li>Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL.</li> <li>Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL.</li> <li>Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams.</li> <li>Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements.</li> <li>Provide technical support to package and board teams by defining SOC pin requirements and facilitating the generation of interposer netlists.</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>Demonstrate proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows.</li> <li>Possess a proven track record in integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards like UCIE, while managing memory and logical functionalities within the SOC RTL.</li> <li>Apply working knowledge of logical equivalency verification for SOC-level subsystem interfaces, collaborating with physical design teams to incorporate floorplan requirements into the RTL.</li> <li>Manage memory wrapper generation, including the integration of DFT wrappers into Subsystem RTL.</li> <li>Provide automation support for generating and configuring SOC RTL with user-defined Subsystems for Design Verification (DV) purposes.</li> <li>Leverage hands-on experience with AI-driven tools to architect automation for SOC integration and facilitate technical support for cross-functional implementation teams.</li> <li>Utilize hands-on experience with design synthesis, linting, clock &amp; reset-domain-crossing, and timing constraint validation to ensure high-quality SOC sign-off.</li> <li>Familiarity with emulation platforms and verification methodologies is highly desirable.</li> </ul> <p><strong>Compensation</strong></p> <p>The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.</p> <ul> <li>Early Career - $120,000 - $275,000 + equity</li> <li>Mid Career - $175,000 - $450,000 + equity&l