Technical Program Manager- Silicon Physical Design

MatX

<p><strong>What MatX Is Building</strong></p> <p>MatX is on a mission to be the compute platform for Artificial General Intelligence. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest Machine Learning workloads for Artificial General Intelligence. </p> <p>MatX is seeking a Technical Program Manager to join our silicon team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for this role  will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.</p> <p><strong>About the Role</strong></p> <p>You will own the cross-functional execution framework for advanced SOC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Develop playbooks and best practices for program management across the PD organization for cross-functional deliveries.</li> <li>Lead end-to-end execution of SoC development programs from concept through production</li> <li>Drive issue resolution during pre-silicon execution, tapeout, bring-up, debug, qualification, and yield learning ensuring physical design readiness. </li> <li>Support silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffs. </li> <li>Build and maintain program trackers, risk registers, and executive dashboards covering each engagement</li> <li>Track technical dependencies,schedule risks, owners, closure dates, critical path, program milestones, tapeout readiness, and silicon bring-up deliverables. schedule risks, owners, closure dates, and escalation paths.</li> <li>Drive gate reviews and weekly program syncs physical design, and validation teams</li> <li>Manage technical risks related to schedule, design maturity, Intellectual Property readiness, verification closure, physical signoff, package/test readiness, and supply chain.</li> <li>Prepare executive-level updates covering milestone health, top risks, decisions needed, critical path, and resource gaps.</li> </ul> <h2><strong>Who you are </strong></h2> <ul> <li>10+ years of technical program management, silicon engineering program management or leading SoC programs through multiple phases of the silicon lifecycle. </li> <li>Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.</li> <li>Experience with program planning, dependency management, milestone tracking, and technical risk management. </li> <li>Experience managing pre-silicon Application Specific Integrated Circuit development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.</li> <li>Experience with pre-silicon validation platforms such as simulation, emulation, Field-Programmable Gate Array prototyping, or hardware/software co-validation.</li> <li>Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.</li> <li>Technical fluency in SoC or chiplet design flows - enough to understand RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases without needing translation</li> <li>Ability to

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